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march 2011 ? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0 1 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module FDMF6705V C xs? drmos C extra-small, high- performance, high-frequency drmos module benefits single 12v input power supply operation ultracompact 6x6mm pqfn, 72% spacesaving compared to conventional discrete solutions fully optimized system efficiency clean switching waveforms with minimal ringing highcurrent handling features over 93% peakefficiency highcurrent handling of 43a highperformance pqfn copper clip package 3state 5v pwm input driver shorter propagation delays than fdmf6704v shorter dead times than fdmf6704v skipmode smod# (lowside gate turn off) input thermal warning flag for overtemperature condition driver output disable function (disb# pin) internal pullup and pulldown for smod# and disb# inputs, respectively fairchild powertrench? technology mosfets for clean voltage waveforms and reduced ringing fairchild syncfet? (integrated schottky diode) technology in the lowside mosfet integrated bootstrap schottky diode adaptive gate drive timing for shootthrough protection undervoltage lockout (uvlo) optimized for switching frequencies up to 1mhz lowprofile smd package fairchild green packaging and rohs compliant based on the intel? 4.0 drmos standard description the xs? drmos family is fairchilds nextgeneration , fully optimized, ultracompact, integrated mosfet p lus driver power stage solutions for highcurrent, high frequency, synchronous buck dcdc applications. the FDMF6705V integrates a driver ic, two power mosfets, and a bootstrap schottky diode into a thermally enhanced, ultracompact 6x6mm pqfn package. with an integrated approach, the complete switching power stage is optimized with regards to driver and mosfet dynamic performance, system inductance, and power mosfet r ds(on) . xs? drmos uses fairchild's highperformance powertrench? mosfet technology, which dramatically reduces switch ringi ng, eliminating the need for a snubber circuit in most buck converter applications. a new driver ic with reduced dead times and propagation delays further enhances the performance of this part. a thermal warning function has been included to warn of a potential overtemperature situation. the FDMF6705V also incorporates features , such as skip mode (smod), for improved lightload efficiency along with a 3state pwm input for compatibility with a wide range of pwm controllers. applications highperformance gaming motherboards compact blade servers, vcore and nonvcore dcdc converters desktop computers, vcore and nonvcore dcdc converters workstations highcurrent dcdc pointofload (pol) converters networking and telecom microprocessor voltage regulators small formfactor voltage regulator modules ordering information part number current rating input voltage switching frequency package top mark FDMF6705V 40a 12v 1000khz 40lead, clipbond pqfn drmos, 6.0x6.0mm package FDMF6705V
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 2 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module typical application circuit figure 1. typical application circuit drmos block diagram figure 2. drmos block diagram smod# pwm vcin vdrv vin pgnd phase gh d boot boot gl cgnd disb# thwn# q1 hs power mosfet input 3state logic r up_pwm v cin v cin v cc uvlo gh logic level shift deadtime control temp. sense 30k 30k gl logic 10a 10a r dn_pwm q2 ls power mosfet vswh v in uvlo 5v ldo v cin smod # pwm vcin vdrv l out c out c vin vin pgnd vswh phase hdrv cgnd d boot boot control ldrv cgnd disbl# thwn# v drv = 8 v to 15 v v in = 3v to 15v q 2 q1 5 v linear reg . temp sense c vdrv c vcin pwm control v cin enabled disabled on off v out v cin
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 3 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module pin configuration figure 3. bottom view figure 4. top view pin definitions pin # name description 1 smod# when smod#=high, the lowside driver is the inverse of pwm input. when smod#=low, the lowside driver is disabled. this pin has a 10 a internal pullup current source. do not leave this pin floating. do not add a noise filter capacitor. 2 vcin linear regulator 5v output. ic bias supply for gate drive output stage. minimum 1f ceramic capacitor is required and should be connected as cl ose as possible from this pin to cgnd 3 vdrv linear regulator input. minimum 1f ceramic capacitor is recommended and should be connected as close as possible from this pin to cgn d. 4 boot bootstrap supply input. provides voltage supply to highside mosfet driver. connect bootstrap capacitor from this pin to phase. 5, 37, 41 cgnd ic ground. ground return for driver ic. 6 gh for manufacturing test only. this pin must flo at. must not be connected to any pin. 7 phase switch node pin for bootstrap capacitor routing. el ectrically shorted to vswh pin. 8 nc no connect. the pin is not electrically connected i nternally, but can be connected to vin for convenience. 9 14, 42 vin power input. output stage supply voltage. 15, 29 35, 43 vswh switch node input. provides return for highside bo otstrapped driver and acts as a sense point for the adaptive shootthrough protection. 16 C 28 pgnd power ground. output stage ground. sou rce pin of lowside mosfet. 36 gl for manufacturing test only. this pin must fl oat. must not be connected to any pin. 38 thwn# thermal warning flag, open collector output. when t emperature exceeds the trip limit, the output is pulled low. thwn# does not disable the mo dule. 39 disb# output disable. when low, this pin disables power m osfet switching (gh and gl are held low). this pin has a 10a internal pulldown curren t source. do not leave this pin floating. do not add a noise filter capacitor. 40 pwm pwm signal input. this pin accepts a 3state logiclevel pwm signal from the controller.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 4 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not rec ommended. in addition, extended exposure to stresses above th e recommended operating conditions may affect devic e reliability. the absolute maximum ratings are stres s ratings only. symbol parameter min. max. unit vcin, disb#, pwm, smod#, gl, thwn# to cgnd pins 6 v vin to pgnd, cgnd pins 25 vdrv to pgnd, cgnd 16 boot, gh to vswh, phase pins 6 boot, vswh, phase, gh to gnd pins 25 boot to vcin pins 22 i o(av) (1) v in =12v, v o =1.0v f sw =300khz 43 a f sw =1mhz 40 jpcb junctiontopcb thermal resistance 3.5 c/w t stg operating and storage temperature range 55 +150 c esd electrostatic discharge protection human body model, jesd22a114 2000 v charged device model, jesd22c101 2000 note: 1. i o(av) is measured in fairchilds evaluation board. this rating can be changed with different application se ttings. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recomme nded operating conditions are specified to ensure optima l performance to the datasheet specifications. fair child does not recommend exceeding them or designing to absolute m aximum ratings. symbol parameter min. typ. max. unit v drv gate drive control circuit input supply voltage 8 12 15 v v in output stage supply voltage (2) 3 12 15 v note: 2. may be operated at lower input voltage.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 5 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module electrical characteristics typical values are v in =12v, v drv =12v, and t a =+25c unless otherwise noted. symbol parameter condition min. typ. max. unit i drv operating current v drv =14v, pwm=low or high or float 2 5 ma internal 5v linear regulator v drv input voltage 8 12 14 v i drv input current 8v ? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 6 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module electrical characteristics (continued) typical values are v in =12v, v drv =12v, and t a =+25c unless otherwise noted. symbol parameter condition min. typ. max. unit thermal warning flag t act activation temperature 150 c t rst reset temperature 135 c r thwn pulldown resistance i pld =5ma 30 250ns timeout circuit t d_timeout timeout delay sw=0v, delay between gh from high to low and gl from low to high 250 ns high-side driver r source_gh output impedance, sourcing source current=100ma 1 r sink_gh output impedance, sinking sink current=100ma 0.8 t r_gh rise time gh=10% to 90%, c load =1.1nf 12 ns t f_gh fall time gh=90% to 10%, c load =1.1nf 11 ns t d_deadon ls to hs deadband time gl going low to gh going high, 2v gl to 10 % gh 10 ns t pd_plghl pwm low propagation delay pwm going low to gh going low, v il_pwm to 90% gh 16 30 ns t pd_phghh pwm high propagation delay (smod held low) pwm going high to gh going high, v ih_pwm to 10% gh (smod=low) 30 ns t pd_tsghh exiting 3state propagation delay pwm (from 3state) going high to gh going high, v ih_pwm to 10% gh 30 ns low-side driver r source_gl output impedance, sourcing source current=100ma 1 r sink_gl output impedance, sinking sink current=100ma 0.5 t r_gl rise time gl=10% to 90%, c load =2.7nf 12 ns t f_gl fall time gl=90% to 10%, c load =2.7nf 8 ns t d_deadoff hs to ls deadband time sw going low to gl going high, 2.2v sw to 10% gl 12 ns t pd_phgll pwmhigh propagation delay pwm going high to gl going low, v ih_pwm to 90% gl 9 25 ns t pd_tsglh exiting 3state propagation delay pwm (from 3state) going low to gl going high, v il_pwm to 10% gl 20 ns boot diode v f forwardvoltage drop i f =10ma 0.35 v v r breakdown voltage i r =1ma 22 v
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 7 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module figure 5. pwm timing diagram t d_deadon pwm sw gh to sw gl t pd_phgll t d_deadoff v ih_pwm v il_pwm 90% 90% 2.0v 10% t pd_plghl 2.2v 10% t d_timeout ( 250ns timeout) 1.2v
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 8 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module typical performance characteristics test conditions: v in =12v, v out =1.0v, v drv =12v, l out =320nh, t a =25c, and natural convection cooling, unless otherwise specified. figure 6. safe operating area figure 7. module powe r loss vs. output current figure 8. power loss vs. switching frequency figure 9. power loss vs. input voltage figure 10. power loss vs. driver supply voltage fig ure 11. power loss vs. output voltage 300khz 1m hz i out =30a f sw =300khz i out =30a f sw =300khz i out =30a f sw =300khz i out =30a
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 9 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module typical performance characteristics (continued) test conditions: v in =12v, v out =1.0v, v drv =12v, l out =320nh, t a =25c, and natural convection cooling, unless otherwise specified. figure 12. power loss vs. output inductance figure 13. driver supply current vs. frequency figure 14. driver supply current vs. driver supply voltage figure 15. driver supply current vs. output current figure 16. uvlo thresholds vs. temperature figure 1 7. ldo line and load regulations f sw =300khz i out =0a f sw =300khz i out =30a i out =0a
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 10 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module typical performance characteristics (continued) test conditions: v in =12v, v out =1.0v, v drv =12v, l out =320nh, t a =25c, and natural convection cooling, unless otherwise specified. figure 18. ldo output voltage vs. temperature figur e 19. pwm thresholds vs. temperature figure 20. disb# thresholds vs. temperature figure 21. smod# thresholds vs. temperature figure 22. boot diode v f vs. temperature
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 11 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module functional description the FDMF6705V is a driverplusfet module optimized for the synchronous buck converter topology. a sing le pwm input signal is all that is required to properl y drive the highside and the lowside mosfets. each part i s capable of driving speeds up to 1mhz. vdrv and disable the vdrv pin is monitored by an undervoltage locko ut (uvlo) circuit. when v drv rises above ~7.3v, the driver is enabled for operation. when v drv falls below ~6.95v, the driver is disabled (gh, gl=0). the driver can a lso be disabled by pulling the disb# pin low (disb# < v il_disb ), which holds both gl and gh low regardless of the pwm input state. the driver can be enabled b y raising the disb# pin voltage high (disb# > v ih_disb ). table 1. uvlo and disable logic uvlo disb# driver state 0 x disabled (gh, gl=0) 1 0 disabled (gh, gl=0) 1 1 enabled (see table 2) 1 open disabled (gh, gl=0) note: 3. disb# has an internal pulldown current source o f 10a. thermal warning flag the FDMF6705V provides a thermal warning flag (thwn) to warn of overtemperature conditions. the thermal warning flag uses an opendrain output that pulls to cgnd when the activation temperature (150 c) is reached. the thwn output returns to a high impedance state once the temperature falls to the r eset temperature (135c). for use, the thwn output requires a pullup resistor, which can be connected to vcin. thwn does not disable the drmos module. figure 23. thwn operation 3-state pwm input the FDMF6705V incorporates a 3state pwm input gate drive design. the 3state gate drive has both logic high level and low level, along with a 3state shutdown window. when the pwm input signal enters and remains within the 3state window for a defined holdoff time (t d_holdoff ), both gl and gh are pulled low. this feature enables the gate drive to shut do wn both highand lowside mosfets to support features such as phase shedding, which is a common feature o n multiphase voltage regulators. operation when exiting 3-state condition when exiting a valid 3state condition, the fdmf670 5v design follows the pwm input command. if the pwm input goes from 3state to low, the low side mosfet is turned on. if the pwm input goes from 3state to high, the highside mosfet is turned on. this is illustrated in figure 24. the FDMF6705V design allo ws for short propagation delays when exiting the 3sta te window ( see electrical characteristics ). low-side driver the lowside driver (gl) is designed to drive a gro und referenced low r ds(on) nchannel mosfet. the bias for gl is internally connected between vcin and cgnd. when the driver is enabled, the driver's outp ut is 180 out of phase with the pwm input. when the driver is disabled (disb#=0v), gl is held low. high-side driver the highside driver is designed to drive a floatin g n channel mosfet. the bias voltage for the highside driver is developed by a bootstrap supply circuit, consisting of the internal schottky diode and exter nal bootstrap capacitor (c boot ). during startup, vswh is held at pgnd, allowing c boot to charge to vcin through the internal diode. when the pwm input goes high, gh begins to charge the gate of the highside mosfet (q1). during this transition, the charge is removed from c boot and delivered to the gate of q1. as q1 turns on, v swh rises to v in , forcing the boot pin to v in + v boot , which provides sufficient v gs enhancement for q1. to complete the switching cycle, q1 is turn ed off by pulling gh to vswh. c boot is then recharged to vcin when vswh falls to pgnd. gh output is in phase with the pwm input. the highside gate is hel d low when the driver is disabled or the pwm signal i s held within the 3state window for longer than the 3 state holdoff time, t d_holdoff . 150 c a ctivation temp. 135 c r eset temp. t j_ driver ic thermal warning n ormal operation high low thwm logic state
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 12 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module adaptive gate drive circuit the driver ic advanced design ensures minimum mosfet deadtime while eliminating potential shoot through (crossconduction) currents. it senses the state of the mosfets and adjusts the gate drive adaptivel y to ensure they do not conduct simultaneously. figur e 24 provides the relevant timing waveforms. to preve nt overlap during the lowtohigh switching transition (q2 off to q1 on), the adaptive circuitry monitors the voltage at the gl pin. when the pwm signal goes high, q2 begins to turn off after some propagation delay (t pd_phgll ). once the gl pin is discharged below ~2v, q1 begins to turn on after adaptive delay t d_deadon . to preclude overlap during the hightolow transiti on (q1 off to q2 on), the adaptive circuitry monitors the voltage at the vswh pin. when the pwm signal goes low, q1 begins to turn off after some propagation delay (t pd_plghl ). once the vswh pin falls below ~2.2v, q2 begins to turn on after adaptive delay t d_deadoff . additionally, v gs(q1) is monitored. when v gs(q1) is discharged below ~1.2v, a secondary adaptive delay is initiated, which results in q2 being driven on afte r t d_timeout , regardless of sw state. this function is implemented to ensure c boot is recharged each switching cycle in the event that the sw voltage do es not fall below the 2.2v adaptive threshold. seconda ry delay t d_timeout is longer than t d_deadoff . . figure 24. pwm and 3-statetiming diagram notes: t pd_xxx = propagation delay from external signal (pwm, smod , etc.) to ic generated signal. example (t pd_phgll - pwm going high to ls vgs (gl) going low). t d_xxx = delay from ic generated signal to ic generated si gnal. example (t d_deadon C ls vgs (gl) low to hs vgs (gh) high). pwm t pd_phgll = pwm rise to gl fall , v ih_pwm to 90% gl t pd_plghl = pwm fall to gh fall, v il_pwm to 90% gh t pd_phghh = pwm rise to gh rise, v ih_pwm to 10% gh (assumes smod held low). smod t pd_slgll = smod fall to gl fall, v il_smod to 90% gl t pd_shglh = smod rise to gl rise, v ih_smod to 10% gl exiting 3-state - t pd_tsghh = pwm 3- state to high to gh rise, v ih_pwm to 10% gh t pd_tsglh = pwm 3- state to low to gl rise, v il_pwm to 10% gl dead times t d_deadon = gl fall to gh rise, ls -comp trip value (~2.0v gl ) to 10% gh t d_deadoff = sw -node fall off to gl rise, sw -comp trip value (~ 2.2v) to 10% gl t pd_tsghh sw gh to sw gl t pd_phgll t d_hold - off 90% l ess than t d_hold -off exit 3- state 2.0v pwm v il_pwm v ih_pwm v tri_hi v ih_pwm v ih_pwm 10% t r_gl t d_hold -off t pd_tsglh l ess than t d_hold -off exit 3-state v ih_pwm v tri_hi v tri_lo v il_pwm t pd_plghl t pd_tsghh dcm t f_ghs t r_gh t d_hold - off 1 0% ccm dcm exit 3-state 90% 10% 9 0% enter 3 -state enter 3 - state t d_deadoff t d_deadon enter 3-state t f_gl v in v out 2.2v
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 13 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module skip mode (smod) the smod function allows for higher converter efficiency under lightload conditions. during smod , the lowside fet gate signal is disabled (held low), preventing discharging of the output capacitors as the filter inductor current attempts reverse current fl ow C also known as diode emulation mode. when the smod pin is pulled high, the synchronous buck converter works in synchronous mode, gating on the lowside fet. when the smod pin is pulled low, the lowside fet is gated off. the smod pin is connected to the pwm controller, which enables or disables the smod automatically when the controller detects lightload condition from output current se nsing. normally this pin is active low. see figure 25 for timing delays . table 2. smod logic disb# pwm smod# gh gl 0 x x 0 0 1 3state x 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 note: 4. the smod feature is intended to have low propagation delay between the smod signal and the lowside fet v gs response time to control diode emulation on a cyclebycycle basis. t d_deadon pwm sw gh to sw gl t pd_phgll t pd_plghl t d_deadoff v ih_pwm v il_pwm 90% 10% 90% 2.2v 2.2v t pd_phghh t pd_shglh delay from smod going high to ls v gs high hs turn-on with smod low. smod# t pd_slgll delay from smod going low to ls v gs low dcm ccm ccm 10% v ih_pwm 10% v out v ih_smod v il_smod 10% figure 25. smod timing diagram 2.0v
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 14 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module application information supply capacitor selection for the supply input (vdrv), a local ceramic bypass capacitor is required to have regulator stable and to reduce noise. for the regulator output on vcin, ano ther local ceramic bypass capacitor is needed to supply the peak power mosfet lowside gate current and boot capacitor charging current. use at least a 1f, x7r or x5r capacitors. keep these capacitors close to the FDMF6705V vdrv and vcin pin and connect them to gnd plane with vias. do not tie vdrv and vcin pins each other. bootstrap circuit the bootstrap circuit uses a charge storage capacit or (c boot ), as shown in figure 26. a bootstrap capacitance of 100nf x7r or x5r capacitor is adequate. a series bootstrap resistor would be need ed for specific applications to improve switching nois e immunity. power loss and efficiency measurement and calculation refer to figure 26 for power loss testing method. p ower loss calculations are: p in =(v in x i in ) + (v drv x i drv ) (w) p sw =v sw x i out (w) p out =v out x i out (w) p loss_module =p in p sw (w) p loss_board =p in p out (w) eff module =100 x p sw /p in (%) eff board =100 x p out /p in (%) figure 26. power loss measurement block diagram vdrv vcin vin pwm v drv disb# pwm input off on c vdrv c vin c boot r boot l out c out a i drv a i in v in v v sw a i out v out thwn boot vswh cgnd pgnd disb# FDMF6705V smod# open drain output phase c v cin
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 15 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module pcb layout guidelines figure 27 provides an example of a proper layout fo r the FDMF6705V and critical components. all of the highcurrent paths, such as v in , v swh , v out , and gnd copper, should be short and wide for low inductance and resistance. this technique aids in achieving a more stable and evenly distributed current flow, along w ith enhanced heat radiation and system performance. the following guidelines are recommendations for th e pcb designer: 1. input ceramic bypass capacitors must be placed close to the vin and pgnd pins. this helps reduce the highcurrent power loop inductance and the input current ripple induced by the power mosfet switching operation. 2. the v swh copper trace serves two purposes. in addition to being the highfrequency current path from the drmos package to the output inductor, it also serves as a heat sink for the lowside mosfet in the drmos package. the trace should be short and wide enough to present a lowimpedance path for the highfrequency, high current flow between the drmos and inductor to minimize losses and temperature rise. note that the vswh node is a high voltage and high frequency switching node with high noise potential. care should be taken to minimize coupling to adjacent traces. since this copper trace also acts as a heat sink for the lower fet, balance using the largest area possible to improve drmos cooling while maintaining acceptable noise emission. 3. an output inductor should be located close to th e FDMF6705V to minimize the power loss due to the vswh copper trace. care should also be taken so the inductor dissipation does not heat the drmos. 4. powertrench? mosfets are used in the output stage. the power mosfets are effective at minimizing ringing due to fast switching. in most cases, no vswh snubber is required. if a snubber is used, it should be placed close to the vswh and pgnd pins. the resistor and capacitor need to be of proper size for the power dissipation. 5. vcin, vdrv, and boot capacitors should be placed as close as possible to the vcin to cgnd, vdrv to cgnd, and boot to phase pins to ensure clean and stable power. routing width and length should be considered as well. 6. include a trace from phase to vswh to improve noise margin. keep the trace as short as possible. 7. the layout should include the option to insert a smallvalue series boot resistor between the boot capacitor and boot pin. the bootloop size, including r boot and c boot , should be as small as possible. the boot resistor is normally not required, but is effective at controlling the high side mosfet turnon slew rate. this can improve noise operating margin in synchronous buck designs that may have noise issues due to ground bounce or high positive and negative vswh ringing. inserting a boot resistance lowers the drmos efficiency. efficiency versus noise trade offs must be considered. the vin and pgnd pins handle large current transients with frequency components greater than 100mhz. if possible, these pins should be connected directly to the vin and board gnd planes. the use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. this added inductance in series with either the vin or pgnd pin degrades system noise immunity by increasing positive and negative vswh ringing. 8. cgnd pad and pgnd pins should be connected by plane gnd copper with multiple vias for stable grounding. poor grounding can create a noise transient offset voltage level between cgnd and pgnd. this could lead to faulty operation of gate driver and mosfet. 9. ringing at the boot pin is most effectively controlled by close placement of the boot capacitor. do not add an additional boot to the pgnd capacitor. this may lead to excess current flow through the boot diode. 10. the smod# and disb# pins have weak internal pullup and pulldown current sources, respectively. they should not be left floating. these pins should not have any noise filter capacitors. 11. use multiple vias on each copper area to interconnect top, inner, and bottom layers to help distribute current flow and heat conduction. vias should be relatively large and of reasonably low inductance. critical highfrequency components, such as r boot , c boot , the rc snubber, and bypass capacitors should be located as close to the respective drmos module pins as possible on the top layer of the pcb. if this is not feasibl e, they should be connected from the backside through a network of lowinductance vias.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 16 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module figure 27. pcb layout example bottom view top view
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 17 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module physical dimensions bottom view land pattern recommendation notes: unless otherwise specified a) does not fully conform to jedec registration mo220, dated may/2005. b) all dimensions are in millimeters. c) dimensions do not include burrs or mold flash. mold flash or burrs does not exceed 0.10mm. d) dimensioning and tolerancing per asme y14.5m1994. e) drawing file name: pqfn40arev2 see detail 'a' detail 'a' scale: 2:1 seating plane 0.65 0.40 2.10 0.50 typ 4.50 5.80 2.50 0.25 1.60 0.60 0.15 2.10 0.35 1 top view front view c 0.30 0.20 0.05 0.00 1.10 0.90 0.10 c 0.08 c 10 11 20 21 30 31 40 0.40 0.50 (0.70) 0.40 2.000.10 2.000.10 (0.20) (0.20) 1.500.10 0.50 0.30 (40x) 0.20 6.00 6.00 0.10 c 2x b a 0.10 c 2x 0.30 0.20 (40x) 4.400.10 0.10 c a b 0.05 c (2.20) 0.50 10 1 40 31 30 21 20 11 pin#1 indicator pin #1 indicator 2.400.10 figure 28. 40-lead, clipbond pqfn drmos, 6.0x6.0mm package package drawings are provided as a service to custo mers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or dat e on the drawing and contact a fairchild semiconduc tor representative to verify or obtain the most recent revision. package specifi cations do not expand the terms of fairchilds worl dwide terms and conditions, specifically the warranty therein, which covers fairchild produc ts. always visit fairchild semiconductors online packa ging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FDMF6705V ? rev. 1.0.1 18 FDMF6705V - xs? drmos - extra-small high-performanc e, high-frequency drmos module

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